library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity round_decode is
    Port ( clk, rst : in std_logic;
	        datain, key : in std_logic_vector (127 downto 0);
           dataout : out std_logic_vector (127 downto 0));
end round_decode;

architecture Behavioral of round_decode is
	signal after_subbytes, after_shiftrows, after_addkey, result : std_logic_vector(127 downto 0);
begin
	InvShiftRows: entity work.invshrows(Behavioral)
		port map (clk => clk,
					 datain => datain,
					 dataout => after_shiftrows);

	Gen_InvSbox:
		for I in 0 to 15 generate
			SubBytes: entity work.invsbox(Behavioral)
				port map (clk => clk, 
							 datain => after_shiftrows(((I + 1)*8 - 1) downto I * 8),
							 dataout => after_subbytes(((I + 1)*8 - 1) downto I * 8));
		end generate Gen_InvSbox;
	
	AddKey: entity work.addkey(Behavioral)
		port map (clk => clk,
					 datain => after_subbytes,
					 subkey => key,
					 dataout => after_addkey);

	Gen_InvMixColumns:
		for J in 0 to 3 generate
			MixColumn: entity work.invmixcol(Structural)
			-- Podlaczanie kolumnami:
			port map (datain(31 downto 24) => after_addkey(103 + J*8 downto 96 + J*8), 
						 datain(23 downto 16) => after_addkey(71 + J*8 downto 64 + J*8), 
						 datain(15 downto 8) => after_addkey(39 + J*8 downto 32 + J*8), 
						 datain(7 downto 0) => after_addkey(7 + J*8 downto 0 + J*8),
						 
						 dataout(31 downto 24) => dataout(103 + J*8 downto 96 + J*8),
						 dataout(23 downto 16) => dataout(71 + J*8 downto 64 + J*8), 
						 dataout(15 downto 8) => dataout(39 + J*8 downto 32 + J*8),
						 dataout(7 downto 0) => dataout(7 + J*8 downto 0 + J*8),
						 
						 clk => clk);
		end generate Gen_InvMixColumns;

	--process(rst)
	--begin
	--	if (rst = '0') then
	--		dataout <= (others => '0');
	--	else
	--		dataout <= result;
	--	end if;
	--end process;

	--process(clk)
	--begin
	--if (rising_edge(clk)) then
	--	
	--end if;
end Behavioral;
